A typical example of a known programmable logic array circuit is illustrated in FIGS. 1 and 2. The programmable logic array circuit illustrated in FIGS. 1 and 2 basically comprises an AND array 1, an OR array 2 and four product term lines 3, 4, 5 and 6. The AND array has six n-channel type MOS field effect transistors 7, 8, 9, 10, 11 and 12 and the OR array 2 has five n-channel type MOS field effect transistors 13, 14, 15, 16 and 17. The product term lines 3 to 6 are coupled in parallel to a source of positive voltage 20 through p-channel type MOS field effect transistors 21, 22, 23 and 24, respectively, and the p-channel type MOS field effect transistors 21 to 24 have respective gate electrodes coupled to the ground terminal so that the p-channel type MOS field effect transistors 21 to 24 serve as load transistors supplying a positive voltage level to the product term lines 3 to 6. The MOS field effect transistors 7 and 10 of the AND array 1 have respective source-drain paths between the product term line 3 and a ground terminal and respective gate electrodes coupled to input signal lines 18 and 19, respectively. The input signal lines 18 and 19 propagate input signals A and B, respectively, so that the product term line 3 has a product signal T1 of a high level only when both of the input signals A and B have respective low levels. Similarly, the MOS field effect transistors 9 and 11 have respective source-drain paths between the product term line 4 and the ground terminal and respective gate electrodes coupled to complementary signal lines 25 and 26, respectively. The complementary signal lines 25 and 26 propagate the inverses of the input signals A and B produced by inverter circuits 27 and 28, respectively, so that the product term line 4 has a product signal T2 of a high level only when both of the input signals A and B have respective high levels. On the other hand, the MOS field effect transistors 12 and 8 have respective source-drain paths between product term lines 5 and 6 and the ground terminal and respective gate electrodes coupled to the complementary signal line 26 and the input signal line 18, respectively. Then, the product term lines 5 has a product signal T3 of a high level when the input signal B has the high level regardless of the input signal A and the product term line 6 has a product signal T4 of a high level when the input signal A has the low level regardless of the input signal B.
The OR array 2 supplies output signal lines 29 and 30 with output signals Q1 and Q2 each having high or low level. Namely, the output signal lines 29 and 30 are coupled in parallel to the source of positive voltage level 20 through p-channel MOS field effect transistors 31 and 32, respectively. The MOS field effect transistors 13 and 14 of the OR array have respective source-drain paths between the output signal line 29 and the ground terminal and respective gate electrodes coupled to the product term lines 3 and 4, respectively. The MOS field effect transistors 13 and 14 thus arranged cause the output line 29 to have the output signal Q1 of the high level only when both of the product signals T1 and T2 on the product term lines 3 and 4 have the respective low levels. Similarly, the MOS field effect transistors 15, 16 and 17 have respective source-drain paths coupled between the output signal line 30 and the ground terminal and respective gate electrodes coupled to the product term lines 4, 5 and 6, respectively. The output signal line 30 thus arranged has the output signal Q2 of the high level only when all of the product signals T2, T3 and T4 on the product term lines 4, 5 and 6 have the respective low levels. The prior-art programmable logic array illustrated in FIG. 1 is operative to produce the output signals Q1 and Q2 represented by the following boolean equations (1) and (2), respectively. EQU Q1=T1+T2=AB+AB (Eq. 1) EQU Q2=T2+T3+T4=AB+B+A (Eq. 2)
Turning to FIG. 3 of the drawings, there is shown the arrangement of the AND array 1 of the programmable logic array illustrated in FIGS. 1 and 2. In FIG. 3, the product term lines 3, 4, 5 and 6 are formed on an intermediate insulating layer overlying a silicon substrate and the input signal lines 18 and 19 and the complementary signal lines 25 and 26 extend over the product term lines 3 to 6 in respective directions substantially perpendicular to the product term lines 3 to 6. The reference numerals 41 to 48 designate n-type diffused regions in a surface portion of the silicon substrate and reference numerals 49 to 64 designate gate electrodes of aluminum. The product term lines 3 and 4 are coupled to the respective side portions of the n-type diffused regions 41, 43, 45 and 47 and the product term lines 5 and 6 are similarly coupled to the respective side portions of the n-type diffused regions 42, 44, 46 and 48. The aluminum gate electrode 49 is coupled to the input signal line 18 through a contact window 65 and an intermediate portion of the n-type diffused regions 41 is electrically coupled to the ground terminal so that the positive charges supplied from the source of positive voltage 20 is discharged to the ground terminal through a left side portion and the intermediate portion of the n-type diffused region 41 when the input signal of the high level is applied from the input signal line 18 to the gate electrode 49 through the contact window 65. Thus, the intermediate portion, the left side portion and the gate electrode 49 forms in combination the MOS type field effect transistor 7 illustrated in FIG. 1. On the other hand, gate electrode 50 is not connected to the input signal line 18 because of lack of a contact window therebetween. This means that the MOS type field effect transistor formed between the input signal line 18 and the product term line 4 does not operate even if the gate electrode 50 is formed. In a similar manner, the MOS type field effect transistor formed between the input signal line 18 and the product term line 5 have no influence on the function of the AND array 1 but the MOS type field effect transistor 8 is provided between the input signal line 18 and the product term line 6. In connection with the inverse signal line 25, the MOS type field effect transistor 9 is formed by an intermediate portion and a right side portion of the n-type diffused region 43 and the gate electrode 54 coupled thereto through a contact window. Further, the MOS type field effect transistor 10 is provided between the input signal line 19 and the product term line 3 because the gate electrode 57 is connected to the input signal line 19 through a contact window but the other MOS type field effect transistors have no influence on the function of the AND array 1. On the other hand, the MOS type field effect transistors 11 and 12 are provided between the complementary signal line 26 and the product term lines 4 and 5, respectively, but another MOS type field effect transistor has no influence on the boolean function. In this manner, the programmable logic array circuit illustrated in FIGS. 1 to 3 realizes the boolean function which is determined by formation of the contact windows during the fabrication process. The AND array 1 illustrated in FIG. 3 is shown in a simple form in FIG. 4 of the drawings. In FIG. 4, the MOS type field effect transistors connected to the signal line 18, 19, 25 or 26 have a circle drawn by a real line but each of the MOS type field effect transistors without connection have a circuit drawn by a broken line.
However, a problem is encountered in the prior-art programmable logic array circuit illustrated in FIGS. 1 to 3 in that the prior-art programmable logic array circuit occupies a large space, which is wasteful of the real estate of the silicon substrate. This is because of the fact that the prior-art programmable logic array circuit needs a large number of MOS type field effect transistors NQ calculated by the following equation (3) whether or not each of the MOS type field effect transistors are used for realizing the predetermined boolean function EQU NQ=2.times.NI.times.NP (Eq. 3)
where NI is the number of the input signal and NP is the number of the product term lines.